1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same. Particularly, this invention relates to a semiconductor device and a method for manufacturing the same for improving alignment accuracy in a photolithography process.
This application is counterpart of Japanese patent application, Serial Number 109378/2003, filed Apr. 14, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
As portable apparatuses have been miniaturized, miniaturization of semiconductor devices aboard portable apparatuses has been demanded. In response to this demand, a semiconductor device called chip size package, having substantially the same outer dimension as the outer dimension of a semiconductor chip, has appeared. As a form of chip size package, there is a semiconductor device called wafer level chip size package or wafer level chip scale package.
Such a wafer level chip size package (hereinafter referred to as WCSP) has a columnar electrode with a relatively large height. (The columnar electrode is also referred to as a post electrode or a bump electrode.) The reason for providing a columnar electrode is to increase the distance between a semiconductor substrate and a mounting board. By increasing this distance, it is possible to relax the stress caused by the difference between the coefficient of thermal expansion of the semiconductor substrate and the coefficient of thermal expansion of the mounting board.
The column are electrode is formed by the following process.
A dry photoresist is formed on an entire semiconductor substrate including redistribution wiring. Through this dry photoresist, the outer shape of a land part (a part that will later become a bottom side of a columnar electrode) of the redistribution wiring is recognized by a mark detector of an optical device such as a stepper. As a result, the position of the land part is recognized by the optical device. On the basis of this position information, alignment between a mask for forming a columnar electrode and the semiconductor substrate (semiconductor wafer) is carried out. (That is, mask alignment is carried out.) Next, the dry photoresist is exposed on the basis of a pattern on the mask. Next, development processing is carried out and the surface of the land part of the redistribution wiring is exposed. On the exposed surface of the landpart, a columnar electrode having a predetermined height is formed by electroplating processing.
In a WCSP dicing process (scribing process), the position of the columnar electrode or the position of an external terminal formed on the columnar electrode is used as a mark for recognizing a dicing position (scribing position). Therefore, if the position where the columnar electrode is to be formed deviates from a preset position (intended position on the redistribution wiring), also the dicing position deviates from a preset position. In short, the position where the columnar electrode is to be formed is one of important elements to decide the accuracy of the dicing process. Therefore, to improve the accuracy of the dicing process, the above-described mask alignment must be carried out accurately.
As a related technique for accurately recognizing a scribing line, for example, there is a technique described in the following literature (see, for example, Patent Literature 1).
Patent Literature 1: Japanese Patent No. 3,065,309 (FIGS. 3 and 4)
However, in WCSP, the columnar electrode having a relatively large height (height: about 100 micrometers (μm)) is necessary for relaxing stress, as described above. Therefore, the dry photoresist for forming the columnar electrode must have a thickness of at least approximately 120 micrometers. In the above-described mask alignment process, since this relatively thick (120-micrometer) dry photoresist exists between the mark detector of the optical device and the land part, the visibility of the land part is not good. Therefore, the accuracy of recognizing the position of the land part by the optical device is lowered. This means that the mask alignment based on the outer shape of the land part of the redistribution wiring increases an error in alignment. As a result, the position where the columnar electrode is to be formed and the dicing position may deviate from preset values.
To improve the accuracy of the above-described mask alignment, it may be considered effective to form a dedicated alignment mark for forming the columnar electrode in an area that is different from the area where the redistribution wiring is formed. However, the provision of the dedicated alignment mark increases the chip size, which is not preferable.
Therefore, a semiconductor device and a method for manufacturing the same that enable improvement in the alignment accuracy without increasing the chip size are desired.
Moreover, a semiconductor device and a method for manufacturing the same that enable improvement in the accuracy of the dicing process are desired.